A vertical DMOSFET has been known as a power MOSFET. See for instance U.S. Pat. No. 4,593,302. The vertical DMOSFET is comprised of a drift region of a first conductivity-type, epitaxially deposited on a semiconductor substrate of the first conductivity-type having low resistance, a gate electrode provided via a gate insulating film disposed on the surface of this drift region, a base region of a second conductivity type and a source region of the first conductivity-type formed by double diffusion, using the gate electrode as a mask, a source electrode that contacts both the source region and the base region, and a drain electrode formed on the rear surface of the substrate.
A trench MOSFET is also known. See for instance U.S. Pat. No. 4,941,026. The trench MOSFET is comprised of a drift region of the first conductivity type epitaxially deposited on a semiconductor substrate of the first conductivity-type having low resistance, a base region of a second conductivity-type disposed on the surface of this drift region, a source region of the first conductivity-type disposed on the surface of this base region, a trench that extends from the surface of this source region through the base region and reaching the drift region, a gate electrode disposed inside this trench via a gate insulating film, a source electrode that contacts both the source region and the base region, and a drain electrode formed on the rear surface of the substrate.
A lateral MOSFET is also known. See for instance Device Design of an Ion Implanted High Voltage MOSFET by Yoshida, et al., Supplement to the Journal of the Japan Society of Applied Physics, Vol. 44, pp. 249-255 (1975). The lateral power MOSFET is comprised of a gate electrode provided via a gate insulating film disposed on the surface of semiconductor substrate of a second conductivity-type that corresponds to the base region, a source region of the first conductivity-type and a relatively lightly doped drift region of the first conductivity-type formed by the self alignment technique using the gate electrode as a mask, a drain region of the first conductivity-type connected to this drift region, a source electrode, and a drain electrode. In a lateral power MOSFET, the source electrode and drain electrode coexist on the same surface of the semiconductor substrate. Therefore, the source electrode and drain electrode are each formed into a comb-tooth shape and are configured in an interdigital manner.
Additionally, a vertical-drain-electrode MOSFET (hereafter referred to as VDE-MOSFET) is known. See for instance A High Power MOSFET with a Vertical Drain Electrode and a Meshed Gate Structure by Yoshida, et al., IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 4, pp. 472-477 (1976). The VDE-MOSFET is comprised of a base region disposed on the surface of a drain region of the first conductivity-type having low resistance, a gate electrode provided via a gate insulating film disposed on the surface of this base region, a source region of the first conductivity-type and a relatively lightly doped drift region of the first conductivity-type formed by the self alignment technique using the gate electrode as a mask, a drain diffusion region interconnected to the drift region and drain region, a source electrode that contacts both the source region and base region, and a drain electrode formed on the rear surface of the substrate.
However, in the above-noted conventional vertical DMOSFET, the on-resistance and the switching time thereof both depend upon the width of the area narrowed by the base region directly underneath the gate electrode. If this width is made narrower, the switching time will be shortened. If this width is made wider, the on-resistance will decrease. In other words, there is a tradeoff between the lower on-resistance and the higher speed switching. Therefore, it is difficult to achieve a level where both are satisfactory.
Moreover, in the above-noted conventional trench MOSFET, the on-resistance can be reduced to less than that of the vertical DMOSFET. However, the overlap area between the gate electrode and the drift region or the drain region will become considerably larger than that of the vertical DMOSFET. Furthermore, because this overlap area largely determines the switching time of a power MOSFET, the switching speed of a trench MOSFET will be slower than that of a vertical DMOSFET.
Moreover, in the above-noted conventional lateral power MOSFET, the aforementioned overlap area is smaller than that of the vertical DMOSFET by approximately a factor of ten. Therefore, it is advantageous for higher speed switching. However, the wiring resistance is large due to the comb-tooth shaped source electrode and drain electrode. Therefore, it is difficult to lower the on-resistance.
The above-noted conventional VDE-MOSFET is devised to decrease the wiring resistance, a drawback of the lateral power MOSFET, without impairing the high-speed switching characteristics of the lateral power MOSFET, and is able to decrease the on-resistance to approximately ⅕ that of the vertical DMOSFET. However, this level of low on-resistance is still insufficient and the realization of even lower on-resistance while maintaining high-speed switching characteristics is necessary.
Accordingly, there is still a need for a MIS semiconductor device and the manufacturing method thereof that greatly improve the relationship between the on-resistance and the switching time by maintaining high-speed switching characteristics while achieving lower on-resistance than in the past.
The present invention relates to MIS semiconductor devices and the manufacturing method thereof. Specifically, the MIS semiconductor devices have a gate formed of a metal (M), an insulator (I), and a semiconductor (S) structure. More specifically, the present invention relates to power MOSFETs and the manufacturing method thereof as representative MIS semiconductor devices for which low on-resistance and high-speed switching are desirable.
One aspect of the present invention is a MIS semiconductor device that includes a semiconductor substrate, a first drain region, a base region, a source region, a gate insulating film, a gate electrode, and a second drain region. It can also include a drift region.
The first drain region can be of a first conductivity-type provided on the first major side of the semiconductor substrate. The base region can be of a second conductivity-type provided on the second major side of the semiconductor substrate. The source region can be of the first conductivity-type selectively formed in the surface portion of the base region. The gate insulating film can be disposed on the surface of the base region, and the gate electrode provided on the gate insulating film. The second drain region, which can serve as drift region, can be disposed in the base region, adjacent to the gate electrode. The second drain region can extend from the surface of the base region to the first drain region, and can even extend completely through the first drain region to contact with a drain electrode formed on the first major side of the substrate.
The drift region can be of the first conductivity-type disposed in the surface portion of the base region. The second drain region can extending through the drift region. The gate electrode can be provided adjacent to the source region, and between the source region and the second drain region. The second drain region can be composed of a heavily doped semiconductor material of the first conductivity-type, a polycrystalline semiconductor material, or a metal.
The MIS device can include an insulation region in the second drain region and a highly conductive region embedded in the insulation region. The highly conductive region can contact the source electrode. The highly conductive region can be adapted to receive a gate potential. The thickness of the insulation region between the highly conductive region and the second drain region can be thicker than the thinnest part of the gate insulating film.
Another aspect of the present invention is a method of manufacturing the MIS semiconductor device. The method can include forming the base region, the source region, the gate insulating film, the gate electrode, and the second drain region, which can be formed by forming a trench through the base region, which trench extends from the second major side of the semiconductor substrate to the first drain region, adjacent to the gate electrode, and forming a second drain region in the trench. The second drain region can be aligned relative to the gate electrode and formed by implanting ions of an impurity of the first conductivity-type using the gate electrode as a mask.
The drift region can be formed on the surface portion of the base region before forming the trench. The trench can be formed through the drift region. The second drain region can be partly formed in the trench. The drift region can be aligned relative to the gate electrode and formed by implanting ions of an impurity of the first conductivity-type using the gate electrode as a mask.